The NTE74HC595 (16−Lead DIP) and NTE74HC595T (SOIC−16) are 8−stage serial shift registers with storage register and 3−state outputs. The registers have separate clocks. These high−speed Si−gate CMOS devices and are pin compatible with Low−power Schottky TTL (LSTTL).

Data is shifted on the positive−going transitions of the shift register clock input (SHCP). The data in each register is transferred to the storage register on a positive−going transition of the storage register clock input (STCP). If both clocks are connected together, th shift register will always be one lock pulse ahead of the storage register.

The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3−state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.